The S-FIL^® technique uses a standard 6-inch x 6-inch x 0.250-inch fused silica blank. During photomask processing the chrome is removed, leaving only the circuit pattern etched into it. The photomask is divided into four quadrants, and the pattern is generated (can be one or more layers). The scheme enables die to die inspection, improving ease of manufacturing. The final template (imprint mask) is sized to a 65 x 65 mm.

During the Step and Flash^® process, the fused silica imprint mask surface is covered with a release layer and is gently pressed into a thin layer of silicon-containing monomer that, upon illumination by a UV lamp, is polymerized into a hard material. The imprint mask is lifted, leaving the circuit pattern on the wafer surface. A residual layer of polymer between features is eliminated by an etch process, and a perfect replica of the pattern is ready to be used in semiconductor processing for etch or deposition. There are multiple mask vendors who are prepared to take orders for S-FIL templates down to 100 nm feature sizes. Only the mask fabrication process, typically accomplished with an e-beam writer, limits the resolution of the features. Features <20 nm have been made to date that exceed the present requirements in the ITRS. Mask cost is less than the current generation of photomasks for several key reasons:

1. No time consuming OPC or PSM data preparation is required.
2. There are no wavelength-related substrate requirements.
3. Pattern generation times are shorter due to the lack of OPC and PSM data volumes.
4. Pattern generation is four times shorter because of smaller field sizes.
5. Parametric yields are higher because of the smaller field sizes.
6. Repair yields are potentially higher because there are no transmission errors to consider.
7. No pellicle is required.

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